University of Tasmania
Browse
1/1
2 files

A Fast VLSI Implementation of a FIFO Queue

conference contribution
posted on 2023-05-23, 03:19 authored by Sale, AHJ, Danielle BerryDanielle Berry, Headlam, A, Loane, RK, John ParryJohn Parry, Wang, TK
The paper describes a hardware implementation in nMOS of a first-in, first-out (FIFO) queue. The implementation has independently operating insertion and extraction logic which is capable of achieving high speeds of less than 20Ons per operation, and may be entirely contained on a single chip. A regular cellular structure is described which is capable of extension both in the direction of wider queued items and in the direction of maximum queue size. The implementation was carried out at the University of Tasmania by the first five authors under the supervision of the last-named author.

History

Publication title

National Conference No 87/5

Editors

Institution of Engineers Australia

Pagination

96-100

Department/School

School of Information and Communication Technology

Publisher

Institution of Engineers Australia

Place of publication

Sydney

Event title

Microelectronics Conference VLSI 1987

Event Venue

Melbourne

Date of Event (Start Date)

1987-04-08

Date of Event (End Date)

1987-04-10

Repository Status

  • Open

Socio-economic Objectives

Computer, electronic and communication equipment not elsewhere classified

Usage metrics

    University Of Tasmania

    Exports

    RefWorks
    BibTeX
    Ref. manager
    Endnote
    DataCite
    NLM
    DC