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A Fast VLSI Implementation of a FIFO Queue


Sale, AHJ and Berry, D and Headlam, A and Loane, RK and Parry, JS and Wang, TK, A Fast VLSI Implementation of a FIFO Queue, National Conference No 87/5, 8-10 April 1987, Melbourne, pp. 96-100. (1987) [Refereed Conference Paper]



The paper describes a hardware implementation in nMOS of a first-in, first-out (FIFO) queue. The implementation has independently operating insertion and extraction logic which is capable of achieving high speeds of less than 20Ons per operation, and may be entirely contained on a single chip. A regular cellular structure is described which is capable of extension both in the direction of wider queued items and in the direction of maximum queue size. The implementation was carried out at the University of Tasmania by the first five authors under the supervision of the last-named author.

Item Details

Item Type:Refereed Conference Paper
Research Division:Engineering
Research Group:Electrical and Electronic Engineering
Research Field:Microelectronics and Integrated Circuits
Objective Division:Manufacturing
Objective Group:Computer Hardware and Electronic Equipment
Objective Field:Computer Hardware and Electronic Equipment not elsewhere classified
UTAS Author:Sale, AHJ (Professor Arthur Sale)
UTAS Author:Berry, D (Ms Danielle Berry)
UTAS Author:Headlam, A (Mr Alexanader Felix Headlam)
UTAS Author:Loane, RK (Mr Richard Kim Loane)
UTAS Author:Parry, JS (Mr John Parry)
UTAS Author:Wang, TK (Mr Tun Kow Wang)
ID Code:34509
Year Published:1987
Deposited By:Computing
Deposited On:2005-07-28
Last Modified:2012-07-10
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